// v08.v
// Verilog version, rewritten by Li Shen, Aug 2002
// Institute of Computing Technology, Chinese Academy of Sciences
// The original VHDL version is b08.vhd from Politecnico di Torino

module b08 (CLOCK,RESET,START,I,O);
input CLOCK;
input RESET;
input START;
input [7:0] I;
output [3:0] O;
/////
wire CLOCK;
wire RESET;
wire START;
wire [7:0] I;
reg [3:0] O;
/////
parameter start_st=0, init=1, loop_st=2, the_end=3;
reg [7:0] IN_R;
reg [3:0] OUT_R;
reg [2:0] MAR;
reg [19:0] temp;
reg [1:0] STATO;
reg [7:0] ROM_1, ROM_2;
reg [3:0] ROM_OR;
/////
function [19:0] ROM;
input [2:0] addr;
begin
  case (addr)
    0: ROM=20'b0111_1111_1001_0111_1010;
    1: ROM=20'b0011_1001_1101_0110_0010;
    2: ROM=20'b1010_1000_1111_1111_1111;
    3: ROM=20'b1111_1111_0110_1011_1010;
    4: ROM=20'b1111_1111_1111_0110_1110;
    5: ROM=20'b1111_1111_1011_1010_1000;
    6: ROM=20'b1100_1010_0111_0101_1011;
    7: ROM=20'b0010_1111_1111_1111_0100;
  endcase
end
endfunction
/////
always @(posedge CLOCK)
begin
  if (RESET)
  begin
    STATO = start_st;
    ROM_1 = 8'b00000000;
    ROM_2 = 8'b00000000;
    ROM_OR = 4'b0000;
    MAR <= 0;
    IN_R <= 8'b00000000;
    OUT_R <= 4'b0000;
    O <= 4'b0000;
  end
  else
    case (STATO)
    start_st:
      if (START)
	STATO = init;

    init:
    begin
      IN_R <= I;
      OUT_R <= 4'b0000;
      MAR <= 0;
      STATO = loop_st;
    end
									
    loop_st:
    begin
      temp = ROM(MAR);
      ROM_1 = temp[19:12];
      ROM_2 = temp[11:4];
      if ((ROM_2 & ~IN_R | ROM_1 & IN_R | ROM_2 & ROM_1)==8'b11111111)
      begin
	ROM_OR = temp[3:0];
	OUT_R <= OUT_R | ROM_OR;
      end
      STATO = the_end;
    end

    the_end:
      if (MAR != 7)
      begin
	MAR <= MAR+1; 
	STATO = loop_st;
      end
      else if (!START)
           begin
	     O <= OUT_R;
	     STATO = start_st;
	   end
			
    endcase
end
endmodule
